
module testdemo;
  reg[3:0] a,b;
  wire c_out;
  reg c_in;
  wire[3:0] sum;
  adder_parallel u(sum,c_out,a,b,c_in);
  initial 
    begin
       c_in=1;
      assign a[3:0]=4'b0101;
      assign b[3:0]=4'b1010;
      #100 assign a[3:0]=4'b1101;
          assign b[3:0]=4'b0111;
          c_in=1;
        #100
        assign a[3:0]=4'b1001;
          assign b[3:0]=4'b0111;
          c_in=0;
    end
endmodule